1. Technical Field
This invention relates generally to the field of semiconductors and, more particularly, to approaches for forming a gate structure on a planar/uniform surface during FinFET device formation.
2. Related Art
As the semiconductor industry attempts to integrate smaller technology, a transition from planar complimentary metal-oxide semiconductor (CMOS) transistors to a three-dimensional (3D) FinFET device architecture has been considered. Relative to planar transistors, FinFETs offer improved channel control and, therefore, reduced short channel effects. When forming FinFET devices, gate structures and/or dummy gates are typically formed on non-planar/topographic surfaces. Specifically, existing approaches form fin surfaces prior to forming gate structures. Such an approach often results in uneven gate formation and degraded device performance.